zener/lvgl_esp32_drivers
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Fix ILI9488 init function | Fix little ILI9488 display artifacts | auto-dma by default for all esp devices | ESP32-S3 support added | updated to be compatible with esp-idf =< 4 and >= 5 versions

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This commit is contained in:
Vitor Alho 2023-09-05 11:24:38 -03:00
parent 26fe6e7703
commit 0b55ade07e
23 changed files with 160 additions and 87 deletions
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12
lvgl_tft/ra8875.c
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@ -156,9 +156,9 @@ void ra8875_init(void)
// Reset the RA8875
gpio_set_level(RA8875_RST, 0);
vTaskDelay(DIV_ROUND_UP(100, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(100, portTICK_DELAY_MS));
gpio_set_level(RA8875_RST, 1);
vTaskDelay(DIV_ROUND_UP(100, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(100, portTICK_DELAY_MS));
#endif
// Initalize RA8875 clocks (SPI must be decelerated before initializing clocks)
@ -251,21 +251,21 @@ void ra8875_sleep_in(void)
ra8875_configure_clocks(false);
ra8875_write_cmd(RA8875_REG_PWRR, 0x00); // Power and Display Control Register (PWRR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_DELAY_MS));
ra8875_write_cmd(RA8875_REG_PWRR, 0x02); // Power and Display Control Register (PWRR)
}
void ra8875_sleep_out(void)
{
ra8875_write_cmd(RA8875_REG_PWRR, 0x00); // Power and Display Control Register (PWRR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_DELAY_MS));
ra8875_configure_clocks(true);
disp_spi_change_device_speed(-1);
ra8875_write_cmd(RA8875_REG_PWRR, 0x80); // Power and Display Control Register (PWRR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_DELAY_MS));
}
uint8_t ra8875_read_cmd(uint8_t cmd)
@ -298,7 +298,7 @@ void ra8875_configure_clocks(bool high_speed)
vTaskDelay(1);
ra8875_write_cmd(RA8875_REG_PCSR, PCSR_VAL); // Pixel Clock Setting Register (PCSR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_DELAY_MS));
}
static void ra8875_set_window(unsigned int xs, unsigned int xe, unsigned int ys, unsigned int ye)