zener/lvgl_esp32_drivers
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fixes for idf 5.x

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This commit is contained in:
hiruna 2023-05-26 22:25:42 +10:00
parent bc57b32d87
commit f8b0f34a59
18 changed files with 84 additions and 83 deletions
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14
lvgl_tft/ra8875.c
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@ -151,14 +151,14 @@ void ra8875_init(void)
// Initialize non-SPI GPIOs
#if RA8875_USE_RST
gpio_pad_select_gpio(RA8875_RST);
gpio_reset_pin(RA8875_RST);
gpio_set_direction(RA8875_RST, GPIO_MODE_OUTPUT);
// Reset the RA8875
gpio_set_level(RA8875_RST, 0);
vTaskDelay(DIV_ROUND_UP(100, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(100, portTICK_PERIOD_MS));
gpio_set_level(RA8875_RST, 1);
vTaskDelay(DIV_ROUND_UP(100, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(100, portTICK_PERIOD_MS));
#endif
// Initalize RA8875 clocks (SPI must be decelerated before initializing clocks)
@ -251,21 +251,21 @@ void ra8875_sleep_in(void)
ra8875_configure_clocks(false);
ra8875_write_cmd(RA8875_REG_PWRR, 0x00); // Power and Display Control Register (PWRR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
ra8875_write_cmd(RA8875_REG_PWRR, 0x02); // Power and Display Control Register (PWRR)
}
void ra8875_sleep_out(void)
{
ra8875_write_cmd(RA8875_REG_PWRR, 0x00); // Power and Display Control Register (PWRR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
ra8875_configure_clocks(true);
disp_spi_change_device_speed(-1);
ra8875_write_cmd(RA8875_REG_PWRR, 0x80); // Power and Display Control Register (PWRR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
}
uint8_t ra8875_read_cmd(uint8_t cmd)
@ -298,7 +298,7 @@ void ra8875_configure_clocks(bool high_speed)
vTaskDelay(1);
ra8875_write_cmd(RA8875_REG_PCSR, PCSR_VAL); // Pixel Clock Setting Register (PCSR)
vTaskDelay(DIV_ROUND_UP(20, portTICK_RATE_MS));
vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
}
static void ra8875_set_window(unsigned int xs, unsigned int xe, unsigned int ys, unsigned int ye)