2018-03-15 15:49:13 +00:00
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2018-04-02 13:20:43 +00:00
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;******************************************************************************
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; * @file STM32_F103RB_MEM_MAP.IC
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; * @author Josef Reisinger
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; * @version V2.0
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; * @date 22-November-2017
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; * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Include File.
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; * This file contains the most important peripheral register's definitions
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; and memory mapping for STM32F10x Performance line,
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2018-03-15 15:49:13 +00:00
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PERIPH_BB_BASE EQU 0x42000000
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2018-04-02 13:20:43 +00:00
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PERIPH_BASE EQU 0x40000000
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APB1PERIPH_BASE EQU PERIPH_BASE
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2018-03-15 15:49:13 +00:00
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APB2PERIPH_BASE EQU PERIPH_BASE + 0x10000
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AHBPERIPH_BASE EQU PERIPH_BASE + 0x20000
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GPIOA_BASE EQU APB2PERIPH_BASE + 0x0800
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GPIOA_CRL EQU GPIOA_BASE
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GPIOA_CRH EQU GPIOA_BASE+0x04
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GPIOA_IDR EQU GPIOA_BASE+0x08
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GPIOA_ODR EQU GPIOA_BASE+0x0c
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GPIOA_BSRR EQU GPIOA_BASE+0x10
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GPIOA_BRR EQU GPIOA_BASE+0x14
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GPIOA_LCKR EQU GPIOA_BASE+0x18
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GPIOB_BASE EQU APB2PERIPH_BASE + 0x0C00
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GPIOB_CRL EQU GPIOB_BASE
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GPIOB_CRH EQU GPIOB_BASE+0x04
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GPIOB_IDR EQU GPIOB_BASE+0x08
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GPIOB_ODR EQU GPIOB_BASE+0x0c
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GPIOB_BSRR EQU GPIOB_BASE+0x10
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GPIOB_BRR EQU GPIOB_BASE+0x14
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GPIOB_LCKR EQU GPIOB_BASE+0x18
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GPIOC_BASE EQU APB2PERIPH_BASE + 0x1000
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GPIOC_CRL EQU GPIOC_BASE
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GPIOC_CRH EQU GPIOC_BASE+0x04
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GPIOC_IDR EQU GPIOC_BASE+0x08
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GPIOC_ODR EQU GPIOC_BASE+0x0c
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GPIOC_BSRR EQU GPIOC_BASE+0x10
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GPIOC_BRR EQU GPIOC_BASE+0x14
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GPIOC_LCKR EQU GPIOC_BASE+0x18
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USART1_BASE EQU APB2PERIPH_BASE + 0x3800
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USART1_SR EQU USART1_BASE
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USART1_DR EQU USART1_BASE+0x04
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USART1_BRR EQU USART1_BASE+0x08
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USART1_CR1 EQU USART1_BASE+0x0C
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USART1_CR2 EQU USART1_BASE+0x10
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USART1_CR3 EQU USART1_BASE+0x14
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USART1_GTPR EQU USART1_BASE+0x18
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2018-04-02 13:20:43 +00:00
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USART2_BASE EQU APB1PERIPH_BASE + 0x4400
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USART2_SR EQU USART2_BASE
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USART2_DR EQU USART2_BASE+0x04
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USART2_BRR EQU USART2_BASE+0x08
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USART2_CR1 EQU USART2_BASE+0x0C
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USART2_CR2 EQU USART2_BASE+0x10
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USART2_CR3 EQU USART2_BASE+0x14
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USART2_GTPR EQU USART2_BASE+0x18
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2018-03-15 15:49:13 +00:00
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RCC_BASE EQU AHBPERIPH_BASE + 0x1000
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RCC_CR EQU RCC_BASE
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RCC_CFGR EQU RCC_BASE+0x04
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RCC_CIR EQU RCC_BASE+0x08
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RCC_APB2RSTR EQU RCC_BASE+0x0C
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RCC_APB1RSTR EQU RCC_BASE+0x10
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RCC_AHBENR EQU RCC_BASE+0x14
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RCC_APB2ENR EQU RCC_BASE+0x18
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RCC_APB1ENR EQU RCC_BASE+0x1C
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RCC_BDCR EQU RCC_BASE+0x20
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RCC_CSR EQU RCC_BASE+0x24
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RCC_AHBRSTR EQU RCC_BASE+0x28
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RCC_CFGR2 EQU RCC_BASE+0x2C
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RCC_APB2ENR_IOPAEN EQU 0x0004
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RCC_APB2ENR_IOPBEN EQU 0x0008
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RCC_APB2ENR_IOPCEN EQU 0x0010
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RCC_APB2ENR_USART1EN EQU 0x4000
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END
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