8d9f6e2548
* Update to support ESP-IDF v5 in develop branch
* Remove the need for rom includes while providing IDF v5 compatibility
* Fix missing '(' typo
* Remove unnecessarily addded rom header files
* Add missing version include
* Fix another forgotten ')'
378 lines
13 KiB
C
378 lines
13 KiB
C
/**
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* @file ra8875.c
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*
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*/
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/*********************
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* INCLUDES
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*********************/
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#include "ra8875.h"
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#include "disp_spi.h"
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#include "driver/gpio.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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/*********************
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* DEFINES
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*********************/
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#define DIV_ROUND_UP(n, d) (((n)+(d)-1)/(d))
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#define SPI_CLOCK_SPEED_SLOW_HZ 1000000
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#define RA8875_MODE_DATA_WRITE (0x00)
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#define RA8875_MODE_DATA_READ (0x40)
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#define RA8875_MODE_CMD_WRITE (0x80)
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#define RA8875_MODE_STATUS_READ (0xC0)
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#define BYTES_PER_PIXEL (LV_COLOR_DEPTH / 8)
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#if defined (LV_HOR_RES_MAX)
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#define HDWR_VAL (LV_HOR_RES_MAX/8 - 1)
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#else
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/* ToDo Remove magic number 256u */
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#define HDWR_VAL (256u/8u - 1u)
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#endif
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#if defined (LV_VER_RES_MAX)
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#define VDHR_VAL (LV_VER_RES_MAX - 1)
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#else
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/* ToDo Remove magic number 128u */
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#define VDHR_VAL (128u - 1u)
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#endif
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#define VDIR_MASK (1 << 2)
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#define HDIR_MASK (1 << 3)
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#ifndef CONFIG_LV_TFT_DISPLAY_CONTROLLER_RA8875
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// Use this settings if there is no Kconfig settings defined
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#define SYSR_VAL (0x00)
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#define DPCR_VAL (0x00)
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#define PCSR_VAL (0x00)
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#define HNDR_VAL (0x00)
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#define HNDFTR_VAL (0x00)
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#define HSTR_VAL (0x00)
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#define HPW (0x00)
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#define HPWR_VAL (0x00)
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#define VNDR_VAL (0x00)
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#define VSTR_VAL (0x00)
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#define VPW (0x00)
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#define VPWR_VAL (0x00)
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#define CONFIG_LV_DISP_RA8875_PLLDIVM (0x00)
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#define CONFIG_LV_DISP_RA8875_PLLDIVN (0x00)
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#define CONFIG_LV_DISP_RA8875_PLLDIVK (0x00)
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#else
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#if (LV_COLOR_DEPTH == 8)
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#define SYSR_VAL (0x00)
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#elif (LV_COLOR_DEPTH == 16)
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#define SYSR_VAL (0x08)
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#else
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#error "Unsupported color depth (LV_COLOR_DEPTH)"
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#endif
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#if ( CONFIG_LV_DISPLAY_ORIENTATION_PORTRAIT_INVERTED || CONFIG_LV_DISPLAY_ORIENTATION_LANDSCAPE_INVERTED )
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#if CONFIG_LV_INVERT_DISPLAY
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#define DPCR_VAL (VDIR_MASK)
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#else
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#define DPCR_VAL (VDIR_MASK | HDIR_MASK)
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#endif
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#else
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#if CONFIG_LV_INVERT_DISPLAY
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#define DPCR_VAL (HDIR_MASK)
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#else
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#define DPCR_VAL (0x00)
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#endif
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#endif
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#if CONFIG_LV_DISP_RA8875_PCLK_INVERT
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#define PCSR_VAL (0x80 | CONFIG_LV_DISP_RA8875_PCLK_MULTIPLIER)
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#else
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#define PCSR_VAL (CONFIG_LV_DISP_RA8875_PCLK_MULTIPLIER)
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#endif
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// Calculate horizontal display parameters
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#if (CONFIG_LV_DISP_RA8875_HORI_NON_DISP_PERIOD >= 260)
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#define HNDR_VAL (31)
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#else
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#define HNDR_VAL ((CONFIG_LV_DISP_RA8875_HORI_NON_DISP_PERIOD-12) / 8)
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#endif
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#define HNDFT (CONFIG_LV_DISP_RA8875_HORI_NON_DISP_PERIOD-(8*HNDR_VAL)-12)
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#if LVGL_DISP_RA8875_DE_POLARITY
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#define HNDFTR_VAL (0x80 | HNDFT)
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#else
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#define HNDFTR_VAL (HNDFT)
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#endif
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#define HSTR_VAL (CONFIG_LV_DISP_RA8875_HSYNC_START/8 - 1)
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#define HPW (CONFIG_LV_DISP_RA8875_HSYNC_PW/8 - 1)
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#if LVGL_DISP_RA8875_HSYNC_POLARITY
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#define HPWR_VAL (0x80 | HPW)
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#else
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#define HPWR_VAL (HPW)
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#endif
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// Calculate vertical display parameters
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#define VNDR_VAL (CONFIG_LV_DISP_RA8875_VERT_NON_DISP_PERIOD - 1)
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#define VSTR_VAL (CONFIG_LV_DISP_RA8875_VSYNC_START - 1)
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#define VPW (CONFIG_LV_DISP_RA8875_VSYNC_PW - 1)
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#if LVGL_DISP_RA8875_VSYNC_POLARITY
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#define VPWR_VAL (0x80 | VPW)
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#else
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#define VPWR_VAL (VPW)
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#endif
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#endif // CONFIG_LV_TFT_DISPLAY_CONTROLLER_RA8875
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/**********************
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* TYPEDEFS
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**********************/
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/**********************
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* STATIC PROTOTYPES
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**********************/
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static void ra8875_configure_clocks(bool high_speed);
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static void ra8875_set_memory_write_cursor(unsigned int x, unsigned int y);
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static void ra8875_set_window(unsigned int xs, unsigned int xe, unsigned int ys, unsigned int ye);
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static void ra8875_send_buffer(uint8_t * data, size_t length, bool signal_flush);
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static void ra8875_reset(void);
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/**********************
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* STATIC VARIABLES
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**********************/
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/**********************
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* MACROS
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**********************/
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/**********************
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* GLOBAL FUNCTIONS
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**********************/
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void ra8875_init(void)
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{
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#ifndef CONFIG_LV_TFT_DISPLAY_CONTROLLER_RA8875
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assert(false); // This driver is not properly configured
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#endif
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unsigned int i = 0;
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struct {
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uint8_t cmd; // Register address of command
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uint8_t data; // Value to write to register
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} init_cmds[] = {
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{RA8875_REG_SYSR, SYSR_VAL}, // System Configuration Register (SYSR)
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{RA8875_REG_HDWR, HDWR_VAL}, // LCD Horizontal Display Width Register (HDWR)
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{RA8875_REG_HNDFTR, HNDFTR_VAL}, // Horizontal Non-Display Period Fine Tuning Option Register (HNDFTR)
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{RA8875_REG_HNDR, HNDR_VAL}, // Horizontal Non-Display Period Register (HNDR)
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{RA8875_REG_HSTR, HSTR_VAL}, // HSYNC Start Position Register (HSTR)
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{RA8875_REG_HPWR, HPWR_VAL}, // HSYNC Pulse Width Register (HPWR)
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{RA8875_REG_VDHR0, VDHR_VAL & 0x0FF}, // LCD Vertical Display Height Register (VDHR0)
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{RA8875_REG_VDHR1, VDHR_VAL >> 8}, // LCD Vertical Display Height Register0 (VDHR1)
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{RA8875_REG_VNDR0, VNDR_VAL & 0x0FF}, // LCD Vertical Non-Display Period Register (VNDR0)
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{RA8875_REG_VNDR1, VNDR_VAL >> 8}, // LCD Vertical Non-Display Period Register (VNDR1)
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{RA8875_REG_VSTR0, VSTR_VAL & 0x0FF}, // VSYNC Start Position Register (VSTR0)
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{RA8875_REG_VSTR1, VSTR_VAL >> 8}, // VSYNC Start Position Register (VSTR1)
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{RA8875_REG_VPWR, VPWR_VAL}, // VSYNC Pulse Width Register (VPWR)
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{RA8875_REG_DPCR, DPCR_VAL}, // Display Configuration Register (DPCR)
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{RA8875_REG_MWCR0, 0x00}, // Memory Write Control Register 0 (MWCR0)
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{RA8875_REG_MWCR1, 0x00}, // Memory Write Control Register 1 (MWCR1)
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{RA8875_REG_LTPR0, 0x00}, // Layer Transparency Register0 (LTPR0)
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{RA8875_REG_LTPR1, 0x00}, // Layer Transparency Register1 (LTPR1)
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};
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#define INIT_CMDS_SIZE (sizeof(init_cmds)/sizeof(init_cmds[0]))
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LV_LOG_INFO("Initializing RA8875...");
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ra8875_reset();
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// Initalize RA8875 clocks (SPI must be decelerated before initializing clocks)
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disp_spi_change_device_speed(SPI_CLOCK_SPEED_SLOW_HZ);
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ra8875_configure_clocks(true);
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disp_spi_change_device_speed(-1);
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// Send all the commands
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for (i = 0; i < INIT_CMDS_SIZE; i++) {
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ra8875_write_cmd(init_cmds[i].cmd, init_cmds[i].data);
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}
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// Perform a memory clear (wait maximum of 100 ticks)
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ra8875_write_cmd(RA8875_REG_MCLR, 0x80);
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for(i = 100; i != 0; i--) {
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if ((ra8875_read_cmd(RA8875_REG_MCLR) & 0x80) == 0x00) {
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break;
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}
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vTaskDelay(1);
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}
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if (i == 0) {
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LV_LOG_WARN("WARNING: Memory clear timed out; RA8875 may be unresponsive.");
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}
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// Enable the display
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ra8875_enable_display(true);
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}
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void ra8875_enable_display(bool enable)
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{
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LV_LOG_INFO("%s display.", enable ? "Enabling" : "Disabling");
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uint8_t val = enable ? (0x80) : (0x00);
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ra8875_write_cmd(RA8875_REG_PWRR, val); // Power and Display Control Register (PWRR)
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}
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void ra8875_flush(lv_disp_drv_t * drv, const lv_area_t * area, lv_color_t * color_map)
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{
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static lv_coord_t x1 = LV_COORD_MIN;
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static lv_coord_t x2 = LV_COORD_MIN;
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static lv_coord_t x = LV_COORD_MIN;
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static lv_coord_t y = LV_COORD_MIN;
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size_t linelen = (area->x2 - area->x1 + 1);
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uint8_t * buffer = (uint8_t*)color_map;
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LV_LOG_INFO("flush: %d,%d at %d,%d", area->x1, area->x2, area->y1, area->y2 );
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// Get lock
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disp_spi_acquire();
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// Set window if needed
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if ((x1 != area->x1) || (x2 != area->x2)) {
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LV_LOG_INFO("flush: set window (x1,x2): %d,%d -> %d,%d", x1, x2, area->x1, area->x2);
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unsigned int ye = 0;
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#if LVGL_VERSION_MAJOR < 8
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ye = LV_VER_RES_MAX - 1;
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#else
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/* ToDo Get y end from driver information */
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#endif
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ra8875_set_window(area->x1, area->x2, 0, ye);
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x1 = area->x1;
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x2 = area->x2;
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}
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// Set cursor if needed
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if ((x != area->x1) || (y != area->y1)) {
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LV_LOG_INFO("flush: set cursor (x,y): %d,%d -> %d,%d", x, y, area->x1, area->y1);
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ra8875_set_memory_write_cursor(area->x1, area->y1);
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x = area->x1;
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}
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// Update to future cursor location
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y = area->y2 + 1;
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lv_coord_t ver_max = 0;
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#if LVGL_VERSION_MAJOR < 8
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ver_max = LV_VER_RES_MAX;
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#else
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/* ToDo Get vertical max from driver information */
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ver_max = lv_disp_get_ver_res((lv_disp_t *) drv);
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#endif
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if (y >= ver_max) {
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y = 0;
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}
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// Write data
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ra8875_send_buffer(buffer, (area->y2 - area->y1 + 1)*BYTES_PER_PIXEL*linelen, true);
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// Release lock
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disp_spi_release();
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}
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void ra8875_sleep_in(void)
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{
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disp_spi_change_device_speed(SPI_CLOCK_SPEED_SLOW_HZ);
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ra8875_configure_clocks(false);
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ra8875_write_cmd(RA8875_REG_PWRR, 0x00); // Power and Display Control Register (PWRR)
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vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
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ra8875_write_cmd(RA8875_REG_PWRR, 0x02); // Power and Display Control Register (PWRR)
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}
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void ra8875_sleep_out(void)
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{
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ra8875_write_cmd(RA8875_REG_PWRR, 0x00); // Power and Display Control Register (PWRR)
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vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
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ra8875_configure_clocks(true);
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disp_spi_change_device_speed(-1);
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ra8875_write_cmd(RA8875_REG_PWRR, 0x80); // Power and Display Control Register (PWRR)
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vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
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}
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uint8_t ra8875_read_cmd(uint8_t cmd)
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{
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uint8_t buf[4] = {RA8875_MODE_CMD_WRITE, cmd, RA8875_MODE_DATA_READ, 0x00};
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disp_spi_transaction(buf, sizeof(buf), (disp_spi_send_flag_t)(DISP_SPI_RECEIVE | DISP_SPI_SEND_POLLING), buf, 0, 0);
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return buf[3];
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}
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void ra8875_write_cmd(uint8_t cmd, uint8_t data)
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{
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uint8_t buf[4] = {RA8875_MODE_CMD_WRITE, cmd, RA8875_MODE_DATA_WRITE, data};
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disp_spi_send_data(buf, sizeof(buf));
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}
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/**********************
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* STATIC FUNCTIONS
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**********************/
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void ra8875_configure_clocks(bool high_speed)
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{
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uint8_t val;
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val = high_speed ? ((CONFIG_LV_DISP_RA8875_PLLDIVM << 7) | CONFIG_LV_DISP_RA8875_PLLDIVN) : 0x07;
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ra8875_write_cmd(RA8875_REG_PLLC1, val); // PLL Control Register 1 (PLLC1)
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vTaskDelay(1);
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val = high_speed ? CONFIG_LV_DISP_RA8875_PLLDIVK : 0x03;
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ra8875_write_cmd(RA8875_REG_PLLC2, val); // PLL Control Register 2 (PLLC2)
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vTaskDelay(1);
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ra8875_write_cmd(RA8875_REG_PCSR, PCSR_VAL); // Pixel Clock Setting Register (PCSR)
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vTaskDelay(DIV_ROUND_UP(20, portTICK_PERIOD_MS));
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}
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static void ra8875_set_window(unsigned int xs, unsigned int xe, unsigned int ys, unsigned int ye)
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{
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ra8875_write_cmd(RA8875_REG_HSAW0, (uint8_t)(xs & 0x0FF)); // Horizontal Start Point 0 of Active Window (HSAW0)
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ra8875_write_cmd(RA8875_REG_HSAW1, (uint8_t)(xs >> 8)); // Horizontal Start Point 1 of Active Window (HSAW1)
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ra8875_write_cmd(RA8875_REG_VSAW0, (uint8_t)(ys & 0x0FF)); // Vertical Start Point 0 of Active Window (VSAW0)
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ra8875_write_cmd(RA8875_REG_VSAW1, (uint8_t)(ys >> 8)); // Vertical Start Point 1 of Active Window (VSAW1)
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ra8875_write_cmd(RA8875_REG_HEAW0, (uint8_t)(xe & 0x0FF)); // Horizontal End Point 0 of Active Window (HEAW0)
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ra8875_write_cmd(RA8875_REG_HEAW1, (uint8_t)(xe >> 8)); // Horizontal End Point 1 of Active Window (HEAW1)
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ra8875_write_cmd(RA8875_REG_VEAW0, (uint8_t)(ye & 0x0FF)); // Vertical End Point of Active Window 0 (VEAW0)
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ra8875_write_cmd(RA8875_REG_VEAW1, (uint8_t)(ye >> 8)); // Vertical End Point of Active Window 1 (VEAW1)
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}
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static void ra8875_set_memory_write_cursor(unsigned int x, unsigned int y)
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{
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ra8875_write_cmd(RA8875_REG_CURH0, (uint8_t)(x & 0x0FF)); // Memory Write Cursor Horizontal Position Register 0 (CURH0)
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ra8875_write_cmd(RA8875_REG_CURH1, (uint8_t)(x >> 8)); // Memory Write Cursor Horizontal Position Register 1 (CURH1)
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ra8875_write_cmd(RA8875_REG_CURV0, (uint8_t)(y & 0x0FF)); // Memory Write Cursor Vertical Position Register 0 (CURV0)
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ra8875_write_cmd(RA8875_REG_CURV1, (uint8_t)(y >> 8)); // Memory Write Cursor Vertical Position Register 1 (CURV1)
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}
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static void ra8875_send_buffer(uint8_t * data, size_t length, bool signal_flush)
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{
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disp_spi_send_flag_t flags = DISP_SPI_SEND_QUEUED | DISP_SPI_ADDRESS_24;
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if (signal_flush) {
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flags |= DISP_SPI_SIGNAL_FLUSH;
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}
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const uint64_t prefix = (RA8875_MODE_CMD_WRITE << 16) // Command write mode
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| (RA8875_REG_MRWC << 8) // Memory Read/Write Command (MRWC)
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| (RA8875_MODE_DATA_WRITE); // Data write mode
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disp_spi_transaction(data, length, flags, NULL, prefix, 0);
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}
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static void ra8875_reset(void)
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{
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#if RA8875_USE_RST
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gpio_set_level(RA8875_RST, 0);
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vTaskDelay(DIV_ROUND_UP(100, portTICK_PERIOD_MS));
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gpio_set_level(RA8875_RST, 1);
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vTaskDelay(DIV_ROUND_UP(100, portTICK_PERIOD_MS));
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#endif
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}
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