321 lines
10 KiB
C
321 lines
10 KiB
C
/**
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* @file disp_spi.c
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*
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*/
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/*********************
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* INCLUDES
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*********************/
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#include "esp_system.h"
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#include "driver/gpio.h"
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#include "driver/spi_master.h"
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#include "esp_log.h"
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#define TAG "disp_spi"
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#include <string.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/semphr.h>
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#include <freertos/task.h>
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#ifdef LV_LVGL_H_INCLUDE_SIMPLE
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#include "lvgl.h"
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#else
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#include "lvgl/lvgl.h"
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#endif
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#include "disp_spi.h"
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#include "disp_driver.h"
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#include "../lvgl_helpers.h"
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#include "../lvgl_spi_conf.h"
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/******************************************************************************
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* Notes about DMA spi_transaction_ext_t structure pooling
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*
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* An xQueue is used to hold a pool of reusable SPI spi_transaction_ext_t
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* structures that get used for all DMA SPI transactions. While an xQueue may
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* seem like overkill it is an already built-in RTOS feature that comes at
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* little cost. xQueues are also ISR safe if it ever becomes necessary to
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* access the pool in the ISR callback.
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*
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* When a DMA request is sent, a transaction structure is removed from the
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* pool, filled out, and passed off to the esp32 SPI driver. Later, when
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* servicing pending SPI transaction results, the transaction structure is
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* recycled back into the pool for later reuse. This matches the DMA SPI
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* transaction life cycle requirements of the esp32 SPI driver.
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*
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* When polling or synchronously sending SPI requests, and as required by the
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* esp32 SPI driver, all pending DMA transactions are first serviced. Then the
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* polling SPI request takes place.
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*
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* When sending an asynchronous DMA SPI request, if the pool is empty, some
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* small percentage of pending transactions are first serviced before sending
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* any new DMA SPI transactions. Not too many and not too few as this balance
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* controls DMA transaction latency.
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*
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* It is therefore not the design that all pending transactions must be
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* serviced and placed back into the pool with DMA SPI requests - that
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* will happen eventually. The pool just needs to contain enough to float some
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* number of in-flight SPI requests to speed up the overall DMA SPI data rate
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* and reduce transaction latency. If however a display driver uses some
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* polling SPI requests or calls disp_wait_for_pending_transactions() directly,
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* the pool will reach the full state more often and speed up DMA queuing.
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*
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*****************************************************************************/
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/*********************
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* DEFINES
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*********************/
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#define SPI_TRANSACTION_POOL_SIZE 50 /* maximum number of DMA transactions simultaneously in-flight */
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/* DMA Transactions to reserve before queueing additional DMA transactions. A 1/10th seems to be a good balance. Too many (or all) and it will increase latency. */
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#define SPI_TRANSACTION_POOL_RESERVE_PERCENTAGE 10
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#if SPI_TRANSACTION_POOL_SIZE >= SPI_TRANSACTION_POOL_RESERVE_PERCENTAGE
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#define SPI_TRANSACTION_POOL_RESERVE (SPI_TRANSACTION_POOL_SIZE / SPI_TRANSACTION_POOL_RESERVE_PERCENTAGE)
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#else
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#define SPI_TRANSACTION_POOL_RESERVE 1 /* defines minimum size */
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#endif
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/**********************
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* TYPEDEFS
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**********************/
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/**********************
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* STATIC PROTOTYPES
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**********************/
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static void IRAM_ATTR spi_ready (spi_transaction_t *trans);
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/**********************
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* STATIC VARIABLES
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**********************/
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static spi_host_device_t spi_host;
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static spi_device_handle_t spi;
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static QueueHandle_t TransactionPool = NULL;
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static transaction_cb_t chained_post_cb;
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/**********************
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* MACROS
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**********************/
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/**********************
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* GLOBAL FUNCTIONS
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**********************/
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void disp_spi_add_device_config(spi_host_device_t host, spi_device_interface_config_t *devcfg)
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{
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spi_host=host;
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chained_post_cb=devcfg->post_cb;
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devcfg->post_cb=spi_ready;
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esp_err_t ret=spi_bus_add_device(host, devcfg, &spi);
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assert(ret==ESP_OK);
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}
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void disp_spi_add_device(spi_host_device_t host)
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{
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disp_spi_add_device_with_speed(host, SPI_TFT_CLOCK_SPEED_HZ);
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}
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void disp_spi_add_device_with_speed(spi_host_device_t host, int clock_speed_hz)
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{
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ESP_LOGI(TAG, "Adding SPI device");
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ESP_LOGI(TAG, "Clock speed: %dHz, mode: %d, CS pin: %d",
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clock_speed_hz, SPI_TFT_SPI_MODE, DISP_SPI_CS);
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spi_device_interface_config_t devcfg={
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.clock_speed_hz = clock_speed_hz,
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.mode = SPI_TFT_SPI_MODE,
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.spics_io_num=DISP_SPI_CS, // CS pin
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.input_delay_ns=DISP_SPI_INPUT_DELAY_NS,
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.queue_size=SPI_TRANSACTION_POOL_SIZE,
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.pre_cb=NULL,
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.post_cb=NULL,
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#if defined(DISP_SPI_HALF_DUPLEX)
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.flags = SPI_DEVICE_NO_DUMMY | SPI_DEVICE_HALFDUPLEX, /* dummy bits should be explicitly handled via DISP_SPI_VARIABLE_DUMMY as needed */
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#else
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#if defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_FT81X)
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.flags = 0,
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#elif defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_RA8875)
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.flags = SPI_DEVICE_NO_DUMMY,
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#endif
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#endif
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};
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disp_spi_add_device_config(host, &devcfg);
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/* create the transaction pool and fill it with ptrs to spi_transaction_ext_t to reuse */
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if(TransactionPool == NULL) {
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TransactionPool = xQueueCreate(SPI_TRANSACTION_POOL_SIZE, sizeof(spi_transaction_ext_t*));
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assert(TransactionPool != NULL);
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for (size_t i = 0; i < SPI_TRANSACTION_POOL_SIZE; i++)
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{
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spi_transaction_ext_t* pTransaction = (spi_transaction_ext_t*)heap_caps_malloc(sizeof(spi_transaction_ext_t), MALLOC_CAP_DMA);
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assert(pTransaction != NULL);
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memset(pTransaction, 0, sizeof(spi_transaction_ext_t));
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xQueueSend(TransactionPool, &pTransaction, portMAX_DELAY);
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}
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}
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}
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void disp_spi_change_device_speed(int clock_speed_hz)
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{
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if (clock_speed_hz <= 0) {
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clock_speed_hz = SPI_TFT_CLOCK_SPEED_HZ;
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}
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ESP_LOGI(TAG, "Changing SPI device clock speed: %d", clock_speed_hz);
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disp_spi_remove_device();
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disp_spi_add_device_with_speed(spi_host, clock_speed_hz);
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}
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void disp_spi_remove_device()
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{
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/* Wait for previous pending transaction results */
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disp_wait_for_pending_transactions();
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esp_err_t ret=spi_bus_remove_device(spi);
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assert(ret==ESP_OK);
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}
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void disp_spi_transaction(const uint8_t *data, size_t length,
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disp_spi_send_flag_t flags, uint8_t *out,
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uint64_t addr, uint8_t dummy_bits)
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{
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if (0 == length) {
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return;
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}
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spi_transaction_ext_t t = {0};
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/* transaction length is in bits */
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t.base.length = length * 8;
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if (length <= 4 && data != NULL) {
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t.base.flags = SPI_TRANS_USE_TXDATA;
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memcpy(t.base.tx_data, data, length);
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} else {
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t.base.tx_buffer = data;
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}
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if (flags & DISP_SPI_RECEIVE) {
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assert(out != NULL && (flags & (DISP_SPI_SEND_POLLING | DISP_SPI_SEND_SYNCHRONOUS)));
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t.base.rx_buffer = out;
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#if defined(DISP_SPI_HALF_DUPLEX)
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t.base.rxlength = t.base.length;
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t.base.length = 0; /* no MOSI phase in half-duplex reads */
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#else
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t.base.rxlength = 0; /* in full-duplex mode, zero means same as tx length */
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#endif
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}
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if (flags & DISP_SPI_ADDRESS_8) {
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t.address_bits = 8;
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} else if (flags & DISP_SPI_ADDRESS_16) {
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t.address_bits = 16;
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} else if (flags & DISP_SPI_ADDRESS_24) {
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t.address_bits = 24;
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} else if (flags & DISP_SPI_ADDRESS_32) {
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t.address_bits = 32;
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}
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if (t.address_bits) {
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t.base.addr = addr;
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t.base.flags |= SPI_TRANS_VARIABLE_ADDR;
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}
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#if defined(DISP_SPI_HALF_DUPLEX)
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if (flags & DISP_SPI_MODE_DIO) {
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t.base.flags |= SPI_TRANS_MODE_DIO;
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} else if (flags & DISP_SPI_MODE_QIO) {
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t.base.flags |= SPI_TRANS_MODE_QIO;
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}
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if (flags & DISP_SPI_MODE_DIOQIO_ADDR) {
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t.base.flags |= SPI_TRANS_MODE_DIOQIO_ADDR;
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}
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if ((flags & DISP_SPI_VARIABLE_DUMMY) && dummy_bits) {
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t.dummy_bits = dummy_bits;
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t.base.flags |= SPI_TRANS_VARIABLE_DUMMY;
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}
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#endif
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/* Save flags for pre/post transaction processing */
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t.base.user = (void *) flags;
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/* Poll/Complete/Queue transaction */
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if (flags & DISP_SPI_SEND_POLLING) {
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disp_wait_for_pending_transactions(); /* before polling, all previous pending transactions need to be serviced */
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spi_device_polling_transmit(spi, (spi_transaction_t *) &t);
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} else if (flags & DISP_SPI_SEND_SYNCHRONOUS) {
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disp_wait_for_pending_transactions(); /* before synchronous queueing, all previous pending transactions need to be serviced */
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spi_device_transmit(spi, (spi_transaction_t *) &t);
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} else {
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/* if necessary, ensure we can queue new transactions by servicing some previous transactions */
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if(uxQueueMessagesWaiting(TransactionPool) == 0) {
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spi_transaction_t *presult;
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while(uxQueueMessagesWaiting(TransactionPool) < SPI_TRANSACTION_POOL_RESERVE) {
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if (spi_device_get_trans_result(spi, &presult, 1) == ESP_OK) {
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xQueueSend(TransactionPool, &presult, portMAX_DELAY); /* back to the pool to be reused */
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}
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}
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}
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spi_transaction_ext_t *pTransaction = NULL;
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xQueueReceive(TransactionPool, &pTransaction, portMAX_DELAY);
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memcpy(pTransaction, &t, sizeof(t));
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if (spi_device_queue_trans(spi, (spi_transaction_t *) pTransaction, portMAX_DELAY) != ESP_OK) {
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xQueueSend(TransactionPool, &pTransaction, portMAX_DELAY); /* send failed transaction back to the pool to be reused */
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}
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}
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}
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void disp_wait_for_pending_transactions(void)
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{
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spi_transaction_t *presult;
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while(uxQueueMessagesWaiting(TransactionPool) < SPI_TRANSACTION_POOL_SIZE) { /* service until the transaction reuse pool is full again */
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if (spi_device_get_trans_result(spi, &presult, 1) == ESP_OK) {
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xQueueSend(TransactionPool, &presult, portMAX_DELAY);
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}
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}
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}
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void disp_spi_acquire(void)
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{
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esp_err_t ret = spi_device_acquire_bus(spi, portMAX_DELAY);
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assert(ret == ESP_OK);
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}
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void disp_spi_release(void)
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{
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spi_device_release_bus(spi);
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}
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/**********************
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* STATIC FUNCTIONS
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**********************/
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static void IRAM_ATTR spi_ready(spi_transaction_t *trans)
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{
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disp_spi_send_flag_t flags = (disp_spi_send_flag_t) trans->user;
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if (flags & DISP_SPI_SIGNAL_FLUSH) {
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lv_disp_t * disp = NULL;
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#if (LVGL_VERSION_MAJOR >= 7)
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disp = _lv_refr_get_disp_refreshing();
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#else /* Before v7 */
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disp = lv_refr_get_disp_refreshing();
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#endif
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lv_disp_flush_ready(&disp->driver);
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}
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if (chained_post_cb) {
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chained_post_cb(trans);
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}
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}
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